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Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights.

, , , , , and . CoRR, (2020)

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Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesign., , , and . PACT, page 36:1-36:15. ACM, (2018)Affinity Alloc: Taming Not-So Near-Data Computing., , , and . MICRO, page 784-799. ACM, (2023)Architectural Simulators Considered Harmful., , , and . IEEE Micro, 35 (6): 4-12 (2015)Domain Specialization Is Generally Unnecessary for Accelerators., , , and . IEEE Micro, 37 (3): 40-50 (2017)A general constraint-centric scheduling framework for spatial architectures., , , , , and . PLDI, page 495-506. ACM, (2013)PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation., , , , and . CoRR, (2023)Exploring the potential of heterogeneous von neumann/dataflow execution models., , and . ISCA, page 298-310. ACM, (2015)Design, integration and implementation of the DySER hardware accelerator into OpenSPARC., , , , , , and . HPCA, page 115-126. IEEE Computer Society, (2012)Pushing the limits of accelerator efficiency while retaining programmability., , , and . HPCA, page 27-39. IEEE Computer Society, (2016)Stream-Dataflow Acceleration., , , and . ISCA, page 416-429. ACM, (2017)