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Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC., , , , , , и . IEEE J. Solid State Circuits, 45 (4): 719-730 (2010)Time-Based Optical Receiver Featuring a Linear Current-to-Time Conversion with Equalization., и . MWSCAS, стр. 713-717. IEEE, (2023)A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp., , , , и . A-SSCC, стр. 345-348. IEEE, (2011)The effect of correlated level shifting on noise performance in switched capacitor circuits., , , и . ISCAS, стр. 942-945. IEEE, (2012)An interstage correlated double sampling technique for switched-capacitor gain stages., , , , и . ISCAS, стр. 1252-1255. IEEE, (2010)Pseudo-differential zero-crossing-based circuit with differential error suppression., и . ISCAS, стр. 1731-1734. IEEE, (2010)Hysteretic Error Extraction in Multi-Level Wireline Receivers., и . ISCAS, стр. 1-5. IEEE, (2021)Robust Timing Error Detection for Multilevel Baud-Rate CDR., и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (10): 3927-3939 (2022)Complexity reduction in multilevel speculative DFEs with unconstrained receiver response., и . Microelectron. J., (2023)26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 444-445. IEEE, (2014)