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A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input.

, , , , , and . NEWCAS, page 1-5. IEEE, (2023)

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A calibration technique for SAR ADC based on code density test., , and . ASICON, page 1-4. IEEE, (2015)A low-offset dynamic comparator with input offset-cancellation., , , , and . ASICON, page 132-135. IEEE, (2017)High speed serial interface transceiver controller based on JESD204B., , , and . NEWCAS, page 1-4. IEEE, (2016)A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (2): 481-494 (2022)A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs., , and . IEEE Trans. Circuits Syst., 67-II (12): 2838-2842 (2020)High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation., , , , and . ISCAS, page 1-5. IEEE, (2023)All-Digital Background Calibration of a Pipelined-SAR ADC Using the "Split ADC" Architecture., , , and . ISCAS, page 1-5. IEEE, (2023)Current-Steering DAC Calibration Using Q-Learning., , , , , and . ISCAS, page 1-5. IEEE, (2023)A statistics-based background capacitor mismatch calibration algorithm for SAR ADC., , , , and . ICTA, page 60-61. IEEE, (2022)A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC., , , , and . ASICON, page 1-4. IEEE, (2015)