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A Modified Joint Geometrical and Statistical Alignment Approach for Low-Resolution Face Recognition.

, , , , and . ICONIP (1), volume 12532 of Lecture Notes in Computer Science, page 88-100. Springer, (2020)

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BCH code based multiple bit error correction in finite field multiplier circuits., , , , and . ISQED, page 615-620. IEEE, (2011)On the Hardware Reduction of z-Datapath of Vectoring CORDIC., , , , and . ISCAS, page 3002-3005. IEEE, (2007)A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields., , , and . ECCTD, page 600-603. IEEE, (2011)Multinomial Memristor Model for Simulations and Analysis., , and . ISED, page 57-61. IEEE Computer Society, (2013)A fast and Effective DFT for test and diagnosis of power switches in SoCs., , , , and . DATE, page 1089-1092. EDA Consortium San Jose, CA, USA / ACM DL, (2013)VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases., , , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 258-269. Springer, (2012)On the design of different concurrent EDC schemes for S-Box and GF(p)., , , , and . ISQED, page 211-218. IEEE, (2010)Secure Testable S-box Architecture for Cryptographic Hardware Implementation., , and . Comput. J., 53 (5): 581-591 (2010)Dual Extended Noise Shaping for High Performance Cross-Coupled Sigma-Delta Modulators., , and . NGMAST, page 209-214. IEEE, (2014)Fusion of evolvable genome structure and multi-objective optimization for subspace clustering., , and . Pattern Recognit., (2019)