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Accelerating Path Planning for Autonomous Driving with Hardware-Assisted Memorization.

, and . ASAP, page 126-130. IEEE, (2022)

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On the performance of averaged optimal routing., , and . CISS, page 1-6. IEEE, (2012)Systematic Security Assessment at an Early Processor Design Stage., , , and . TRUST, volume 6740 of Lecture Notes in Computer Science, page 154-171. Springer, (2011)Using Information Flow to Design an ISA that Controls Timing Channels., , and . CSF, page 272-287. IEEE, (2019)Towards Fast, Adaptive, and Hardware-Assisted User-Space Scheduling., , , , , , , , and . CoRR, (2023)Execution time prediction for energy-efficient hardware accelerators., , and . MICRO, page 457-469. ACM, (2015)Verifiable Access Control for Augmented Reality Localization and Mapping., , , , , , and . CoRR, (2022)AEGIS: a single-chip secure processor.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2005)ndltd.org (oai:dspace.mit.edu:1721.1/34469).GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning., , , and . CoRR, (2020)MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration., , , and . CoRR, (2020)Information Flow Control in Machine Learning through Modular Model Architecture., , , , , , , , , and . CoRR, (2023)