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Disambiguation of "Giri, Davide"

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Runtime reconfigurable memory hierarchy in embedded scalable platforms.

, , and . ASP-DAC, page 719-726. ACM, (2019)

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Shibashish Giri

Wolfgang Girisch

Philipp Girichidis

Joseph Girisch

Jana Girisch

 

Other publications of authors with the same name

The MosaicSim Simulator (Full Technical Report)., , , , , , , , , and . CoRR, (2020)Accelerators and Coherence: An SoC Perspective., , and . IEEE Micro, 38 (6): 36-45 (2018)SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs., , , , , , , , and . IEEE Des. Test, 40 (6): 64-75 (December 2023)DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET., , , , , , , , , and 7 other author(s). CICC, page 1-2. IEEE, (2023)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)Agile SoC Development with Open ESP : Invited Paper., , , , , , , , and . ICCAD, page 96:1-96:9. IEEE, (2020)PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs., , , , and . DATE, page 1-6. IEEE, (2023)Parallel and Serial Computation in Nanomagnet Logic: An Overview., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (8): 1427-1437 (2018)Runtime reconfigurable memory hierarchy in embedded scalable platforms., , and . ASP-DAC, page 719-726. ACM, (2019)Accelerators & Security: The Socket Approach., , and . IEEE Comput. Archit. Lett., 21 (2): 65-68 (2022)