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A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)

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Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs., , , , , and . ISCAS, page 1-5. IEEE, (2019)A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array., , , , , , , , , and 2 other author(s). BioCAS, page 1-4. IEEE, (2018)Real-time correction of wide-angle lens distortion for images with GPU computing., , , and . APCCAS, page 456-459. IEEE, (2012)ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2533-2545 (2019)Effective forgery detection using DCT+SVD-based watermarking for region of interest in key frames of vision-based surveillance., and . Int. J. Comput. Sci. Eng., 8 (4): 297-305 (2013)Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (10): 2962-2965 (2017)Conditional Activation for Diverse Neurons in Heterogeneous Networks., , , , , , and . CoRR, (2018)A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate., , , , , , , , , and 3 other author(s). ISSCC, page 402-404. IEEE, (2019)Pixel-Wise Prediction based Visual Odometry via Uncertainty Estimation., , , and . WACV, page 2517-2527. IEEE, (2023)Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter., , and . ITC, page 1-8. IEEE, (2020)