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Learning-based prediction of embedded memory timing failures during initial floorplan design.

W. Chan, K. Chung, A. Kahng, N. MacDonald, and S. Nath. ASP-DAC, page 178-185. IEEE, (2016)

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Wei-Ting Liu

Carolyn Wei Ji Chan

M Tingart

Wen-tsi Ting

Wei Wei

Other publications of authors with the same name

3DIC benefit estimation and implementation guidance from 2DIC implementation.W. Chan, S. Nath, A. Kahng, Y. Du, and K. Samadi. DAC, page 30:1-30:6. ACM, (2015)Revisiting 3DIC benefit with multiple tiers.W. Chan, A. Kahng, and J. Li. Integr., (2017)ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap.J. Carballo, W. Chan, P. Gargini, A. Kahng, and S. Nath. ICCD, page 139-146. IEEE Computer Society, (2014)Learning-based prediction of embedded memory timing failures during initial floorplan design.W. Chan, K. Chung, A. Kahng, N. MacDonald, and S. Nath. ASP-DAC, page 178-185. IEEE, (2016)BEOL stack-aware routability prediction from placement using data mining techniques.W. Chan, Y. Du, A. Kahng, S. Nath, and K. Samadi. ICCD, page 41-48. IEEE Computer Society, (2016)Statistical analysis and modeling for error composition in approximate computation circuits.W. Chan, A. Kahng, S. Kang, R. Kumar, and J. Sartori. ICCD, page 47-53. IEEE Computer Society, (2013)Methodology for electromigration signoff in the presence of adaptive voltage scaling.W. Chan, A. Kahng, and S. Nath. SLIP, page 6:1-6:7. IEEE Computer Society, (2014)On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling.T. Chan, W. Chan, and A. Kahng. IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (10): 2920-2930 (2014)ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning.T. Chan, W. Chan, and A. Kahng. ICCD, page 269-272. IEEE Computer Society, (2017)Trading Accuracy for Energy in Stochastic Circuit Design.A. Alaghi, W. Chan, J. Hayes, A. Kahng, and J. Li. ACM J. Emerg. Technol. Comput. Syst., 13 (3): 47:1-47:30 (2017)

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Disambiguation of "Chan, Wei-Ting Jonas"

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Learning-based prediction of embedded memory timing failures during initial floorplan design.

Please choose a person to relate this publication to

Wei-Ting Liu

Carolyn Wei Ji Chan

M Tingart

Wen-tsi Ting

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chan, Wei-Ting Jonas"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Learning-based prediction of embedded memory timing failures during initial floorplan design.

Please choose a person to relate this publication to

Wei-Ting Liu

Carolyn Wei Ji Chan

M Tingart

Wen-tsi Ting

Wei Wei

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Learning-based prediction of embedded memory timing failures during initial floorplan design.