Author of the publication

A Class of Graphs for Fault-Tolerant Processor Interconnections.

, and . ICDCS, page 448-460. IEEE Computer Society, (1984)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Fast Optimal Robust Path Delay Fault Testable Adder., , , and . ED&TC, page 491-499. IEEE Computer Society, (1996)On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem., and . ED&TC, page 380-387. IEEE Computer Society, (1996)Universal delay test sets for logic networks., , and . IEEE Trans. Very Large Scale Integr. Syst., 7 (2): 156-166 (1999)A Construction for Convolutional Codes Using Block Codes, and . Inf. Control., 12 (1): 55-70 (January 1968)A Decoding Algorithm for Some Convolutional Codes Constructed from Block Codes, and . Inf. Control., 13 (5): 492-507 (November 1968)Guaranteed convergence in a class of Hopfield networks., , and . IEEE Trans. Neural Networks, 3 (6): 951-961 (1992)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design., , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 42:1-42:19 (2019)Correcting Unidirectional Errors with Nonpositive Hopfield Networks., , and . ICNN, page 2933-2938. IEEE, (1995)Embedded Totally Self-Checking Checkers: A Practical Design., and . IEEE Des. Test Comput., 7 (4): 5-12 (1990)Augmented Shuffle-Exchange Multistage Interconnection Networks., and . Computer, 20 (6): 30-40 (1987)