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Disambiguation of "Karmakar, Rajit"

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Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure.

, , and . ISCAS, page 1-5. IEEE, (2019)

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Adyanath Karmakar

Rajit Rajappa

Biswajit Karmakar

Anupam Karmakar

Shreya Karmakar

 

Other publications of authors with the same name

Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption., , and . IEEE Trans. Emerg. Top. Comput., 9 (4): 2109-2124 (2021)Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling., and . Integr., (2015)Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure., , and . ISCAS, page 1-5. IEEE, (2019)A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis., , and . DAC, page 90. ACM, (2019)Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model., , and . VDAT, page 1-6. IEEE, (2014)A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection., , and . Integr., (2020)Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits., , and . CoRR, (2018)Thermal-Safe Schedule Generation for System-on-Chip Testing., and . VLSID, page 475-480. IEEE Computer Society, (2016)On Finding Suitable Key-Gate Locations In Logic Encryption., , and . ISCAS, page 1-5. IEEE, (2018)Temperature and data size trade-off in dictionary based test data compression., and . Integr., (2017)