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Disambiguation of "Chattopadhyay, Santanu"

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Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure.

, , and . ISCAS, page 1-5. IEEE, (2019)

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Anupam Chattopadhyay

Santanu Sarma

Santanu Mukherjee

Dhrupadi Chattopadhyay

Santanu Pal

 

Other publications of authors with the same name

Low power finite state machine synthesis using power-gating., , and . Integr., 44 (3): 175-184 (2011)Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption., , and . IEEE Trans. Emerg. Top. Comput., 9 (4): 2109-2124 (2021)Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip., , , and . CoRR, (2019)Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution., , and . Integr., (2018)Reliability-aware application mapping onto mesh based Network-on-Chip., , and . Integr., (2018)Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing., , and . Integr., 45 (2): 211-221 (2012)Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling., and . Integr., (2015)Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (7): 1185-1195 (2015)In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 393-397 (2016)Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach., , , , , and . ICIT, page 228-233. IEEE, (2019)