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Multiple target performance evaluation model for HD video encoder VLSI architecture design.

, , and . VCIP, page 1-4. IEEE, (2013)

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Lossless image compression algorithm and hardware architecture for bandwidth reduction of external memory., , , and . IET Image Processing, 11 (6): 379-388 (2017)Motion Vector Smoothing for True Motion Estimation., , , , and . ICASSP (2), page 241-244. IEEE, (2006)A Fast Zero-Quantized Percentage Model for Video Coding with RDO Quantization., , and . PCM (3), volume 11166 of Lecture Notes in Computer Science, page 761-771. Springer, (2018)A hardware-efficient architecture for multi-resolution motion estimation using fully reconfigurable processing element array., , , , and . ICME, page 1-6. IEEE Computer Society, (2011)VLSI friendly me search window buffer structure optimization and algorithm verification for high definition H.264/AVS video encoder., , , and . ICME, page 1098-1101. IEEE, (2009)An Efficient Lossless Image Compression Algorithm for External Memory Bandwidth Saving., and . DCC, page 435. IEEE, (2014)High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder., , , , and . VCIP, volume 7744 of SPIE Proceedings, page 77441W. SPIE, (2010)A Regular VLSI Architecture of Motion Vector Prediction for Multiple-Standard MPEG-Like Video Codec., , , and . J. Signal Process. Syst., 76 (1): 47-62 (2014)A practical consistent-quality two-pass VBR video coding algorithm for digital storage application., , , and . IEEE Trans. Consumer Electronics, 50 (4): 1142-1150 (2004)Adaptive integer-precision Lagrange multiplier selection for high performance AVS video coding., , , and . VCIP, page 1-4. IEEE, (2011)