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Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications.

P. Sikka, A. Asati, и C. Shekhar. Circuits Syst. Signal Process., 40 (6): 2883-2894 (2021)

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Karan Sikka

Prateek Saxena

Aime Sikkar

Другие публикации лиц с тем же именем

Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm.P. Sikka, A. Asati, и C. Shekhar. Microprocess. Microsystems, (2021)Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA.S. Pandit, и P. Sikka. ICCCNT, стр. 1-5. IEEE, (2018)High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications.P. Sikka, A. Asati, и C. Shekhar. Comput. Intell., 37 (3): 1056-1067 (2021)Speed optimal FPGA implementation of the encryption algorithms for telecom applications.P. Sikka, A. Asati, и C. Shekhar. Microprocess. Microsystems, (2020)Hashed Access Policy-Based Secure Data Transmission Using SDHAK-ECC.P. Sikka. Int. J. Cooperative Inf. Syst., 31 (3&4): 2350001:1-2350001:21 (декабря 2022)Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications.P. Sikka, A. Asati, и C. Shekhar. Circuits Syst. Signal Process., 40 (6): 2883-2894 (2021)High-Level synthesis assisted design and verification framework for automotive radar processors.P. Sikka, A. Asati, и C. Shekhar. Microprocess. Microsystems, (2020)Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis.P. Sikka, A. Asati, и C. Shekhar. Wirel. Pers. Commun., 127 (3): 1869-1878 (2022)

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