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%0 Conference Paper
%1 conf/glvlsi/RyanWC07
%A Ryan, Joseph F.
%A Wang, Jiajing
%A Calhoun, Benton H.
%B ACM Great Lakes Symposium on VLSI
%D 2007
%E Zhou, Hai
%E Macii, Enrico
%E Yan, Zhiyuan
%E Massoud, Yehia
%I ACM
%K dblp
%P 275-280
%T Analyzing and modeling process balance for sub-threshold circuit design.
%U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2007.html#RyanWC07
%@ 978-1-59593-605-9
@inproceedings{conf/glvlsi/RyanWC07,
added-at = {2018-11-06T00:00:00.000+0100},
author = {Ryan, Joseph F. and Wang, Jiajing and Calhoun, Benton H.},
biburl = {https://www.bibsonomy.org/bibtex/27684c69dabf306a6cf3abe6042262267/dblp},
booktitle = {ACM Great Lakes Symposium on VLSI},
crossref = {conf/glvlsi/2007},
editor = {Zhou, Hai and Macii, Enrico and Yan, Zhiyuan and Massoud, Yehia},
ee = {https://doi.org/10.1145/1228784.1228853},
interhash = {0ccff6686d6df33c4bd2de7f58383dcd},
intrahash = {7684c69dabf306a6cf3abe6042262267},
isbn = {978-1-59593-605-9},
keywords = {dblp},
pages = {275-280},
publisher = {ACM},
timestamp = {2024-04-09T22:51:08.000+0200},
title = {Analyzing and modeling process balance for sub-threshold circuit design.},
url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2007.html#RyanWC07},
year = 2007
}