%0 Conference Paper %1 conf/isqed/UttraphanSH14 %A Uttraphan, Chessda %A Shaikh-Husin, Nasir %A Hani, Mohamed Khalil %B ISQED %D 2014 %I IEEE %K dblp %P 357-364 %T An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design. %U http://dblp.uni-trier.de/db/conf/isqed/isqed2014.html#UttraphanSH14 %@ 978-1-4799-3945-9

@inproceedings{conf/isqed/UttraphanSH14, added-at = {2021-05-24T00:00:00.000+0200}, author = {Uttraphan, Chessda and Shaikh-Husin, Nasir and Hani, Mohamed Khalil}, biburl = {https://www.bibsonomy.org/bibtex/2cddcc07b77778748cbe56ed2baab201b/dblp}, booktitle = {ISQED}, crossref = {conf/isqed/2014}, ee = {https://doi.org/10.1109/ISQED.2014.6783348}, interhash = {1a184831eb8380c0a9017778e7b8593a}, intrahash = {cddcc07b77778748cbe56ed2baab201b}, isbn = {978-1-4799-3945-9}, keywords = {dblp}, pages = {357-364}, publisher = {IEEE}, timestamp = {2024-04-10T14:08:31.000+0200}, title = {An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design.}, url = {http://dblp.uni-trier.de/db/conf/isqed/isqed2014.html#UttraphanSH14}, year = 2014 }