%0 Conference Paper %1 conf/ats/MajumdarJCL17 %A Majumdar, Amitava %A Jayadev, Balakrishna %A Cheng, Da %A Lin, Albert %B ATS %D 2017 %I IEEE Computer Society %K dblp %P 139-144 %T Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. %U http://dblp.uni-trier.de/db/conf/ats/ats2017.html#MajumdarJCL17 %@ 978-1-5386-2437-1

@inproceedings{conf/ats/MajumdarJCL17, added-at = {2024-04-18T00:00:00.000+0200}, author = {Majumdar, Amitava and Jayadev, Balakrishna and Cheng, Da and Lin, Albert}, biburl = {https://www.bibsonomy.org/bibtex/2a5c02efaf39bdf30a10821fa14510a6c/dblp}, booktitle = {ATS}, crossref = {conf/ats/2017}, ee = {https://doi.ieeecomputersociety.org/10.1109/ATS.2017.36}, interhash = {2f16c2edcf6a6329ddff93e250118a24}, intrahash = {a5c02efaf39bdf30a10821fa14510a6c}, isbn = {978-1-5386-2437-1}, keywords = {dblp}, pages = {139-144}, publisher = {IEEE Computer Society}, timestamp = {2024-04-22T07:44:10.000+0200}, title = {Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.}, url = {http://dblp.uni-trier.de/db/conf/ats/ats2017.html#MajumdarJCL17}, year = 2017 }