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Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.

A. Majumdar, B. Jayadev, D. Cheng, and A. Lin. ATS, page 139-144. IEEE Computer Society, (2017)

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Lin Lin

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Generating Formal Safety Assurances for High-Dimensional Reachability.A. Lin, and S. Bansal. CoRR, (2022)Taiwan foundry for system-in-package (SIP).A. Lin. ASP-DAC, page 197-204. ACM, (2000)Demixing Calcium Imaging Data in C. elegans via Deformable Non-negative Matrix Factorization.A. Nejatbakhsh, E. Varol, E. Yemini, V. Venkatachalam, A. Lin, A. Samuel, O. Hobert, and L. Paninski. MICCAI (5), volume 12265 of Lecture Notes in Computer Science, page 14-24. Springer, (2020)Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.N. Patil, A. Lin, J. Zhang, H. Wong, and S. Mitra. DAC, page 304-309. ACM, (2009)Carbon nanotube circuits: Living with imperfections and variations.J. Zhang, N. Patil, A. Lin, H. Wong, and S. Mitra. DATE, page 1159-1164. IEEE Computer Society, (2010)Connectome-constrained Latent Variable Model of Whole-Brain Neural Activity.L. Mi, R. Xu, S. Prakhya, A. Lin, N. Shavit, A. Samuel, and S. Turaga. ICLR, OpenReview.net, (2022)Sensor platforms for multimodal underwater monitoring.R. Kastner, A. Lin, C. Schurgers, J. Jaffe, P. Franks, and B. Stewart. IGCC, page 1-7. IEEE Computer Society, (2012)Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.A. Majumdar, B. Jayadev, D. Cheng, and A. Lin. ATS, page 139-144. IEEE Computer Society, (2017)Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.H. Wei, J. Zhang, L. Wei, N. Patil, A. Lin, M. Shulaker, H. Chen, H. Wong, and S. Mitra. ICCAD, page 227-230. IEEE Computer Society, (2011)The DARPA High-Performance Knowledge Bases Project.P. Cohen, R. Schrag, E. Jones, A. Pease, A. Lin, B. Starr, D. Gunning, and M. Burke. AI Magazine, 19 (4): 25-49 (1998)

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Disambiguation of "Lin, Albert"

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Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Albert"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
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Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.