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Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.

, , , и . ATS, стр. 139-144. IEEE Computer Society, (2017)

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Amitava Roy

Amitava Chatterjee

Sudipta Majumdar

Amitava Chatterjee

Amitava Chatterjee

 

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