%0 Conference Paper %1 conf/asicon/LiuSMFZ13 %A Liu, Cong %A Shen, Weiwei %A Ma, Tianlong %A Fan, Yibo %A Zeng, Xiaoyang %B ASICON %D 2013 %I IEEE %K dblp %P 1-4 %T A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2013.html#LiuSMFZ13 %@ 978-1-4673-6415-7

@inproceedings{conf/asicon/LiuSMFZ13, added-at = {2015-02-23T00:00:00.000+0100}, author = {Liu, Cong and Shen, Weiwei and Ma, Tianlong and Fan, Yibo and Zeng, Xiaoyang}, biburl = {https://www.bibsonomy.org/bibtex/24886438709e29de869cfc0489c20b4c9/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2013}, ee = {http://dx.doi.org/10.1109/ASICON.2013.6811849}, interhash = {31d8d6c2125796b0855dcb3552633183}, intrahash = {4886438709e29de869cfc0489c20b4c9}, isbn = {978-1-4673-6415-7}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2015-06-19T16:17:58.000+0200}, title = {A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2013.html#LiuSMFZ13}, year = 2013 }