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A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.

C. Liu, W. Shen, T. Ma, Y. Fan, and X. Zeng. ASICON, page 1-4. IEEE, (2013)

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Xiaoyang Wang

Xiaoyang Gao

Jian Zeng

Gang Zeng

Lecai Zeng

Other publications of authors with the same name

A fast multi-core virtual platform and its application on software development.Z. Wang, D. Zhang, X. Yu, Z. Yu, and X. Zeng. ASICON, page 1-4. IEEE, (2013)A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.C. Liu, W. Shen, T. Ma, Y. Fan, and X. Zeng. ASICON, page 1-4. IEEE, (2013)A 2D mesh NoC with self-configurable and shared-FIFOs routers.W. Zhou, J. Yu, J. Lin, Z. Yu, and X. Zeng. ASICON, page 1-4. IEEE, (2013)Low-complexity two-stage timing acquisition scheme for UWB communications.Y. Peng, L. Mai, and X. Zeng. WTS, page 53-56. IEEE, (2008)An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems.N. Ding, C. Chen, W. Fan, Y. Chen, and X. Zeng. ISCAS, page 1516-1519. IEEE, (2012)Low power design for FIR filter.G. Xu, Y. Zou, J. Han, and X. Zeng. ASICON, page 1-4. IEEE, (2013)Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation.J. Zhao, J. Han, X. Zeng, and Y. Deng. SiPS, page 151-156. IEEE, (2007)Optimized digital automatic gain control for DVB-S2 system.Y. Zhang, J. Cao, C. Wu, J. Han, and X. Zeng. WTS, page 1-5. IEEE, (2010)Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm.Y. Pang, Y. Zhang, J. Han, and X. Zeng. ASICON, page 561-564. IEEE, (2017)Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications.H. Chang, W. Lu, X. Cheng, Y. Guo, and X. Zeng. ASICON, page 465-468. IEEE, (2011)

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Disambiguation of "Zeng, Xiaoyang"

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A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.

Please choose a person to relate this publication to

Xiaoyang Wang

Xiaoyang Gao

Jian Zeng

Gang Zeng

Lecai Zeng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zeng, Xiaoyang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.

Please choose a person to relate this publication to

Xiaoyang Wang

Xiaoyang Gao

Jian Zeng

Gang Zeng

Lecai Zeng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.