%0 Conference Paper %1 conf/isscc/ClintonSTZSC18 %A Clinton, Michael %A Singh, Rajinder %A Tsai, Marty %A Zhang, Shayan %A Sheffield, Bryan %A Chang, Jonathan %B ISSCC %D 2018 %I IEEE %K dblp %P 200-201 %T A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2018.html#ClintonSTZSC18 %@ 978-1-5090-4940-0

@inproceedings{conf/isscc/ClintonSTZSC18, added-at = {2018-03-14T00:00:00.000+0100}, author = {Clinton, Michael and Singh, Rajinder and Tsai, Marty and Zhang, Shayan and Sheffield, Bryan and Chang, Jonathan}, biburl = {https://www.bibsonomy.org/bibtex/280d6e95323bbd3c48206eae7b1573fe0/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2018}, ee = {https://doi.org/10.1109/ISSCC.2018.8310253}, interhash = {45782d8c5fd27c07b24ccf19aa647d37}, intrahash = {80d6e95323bbd3c48206eae7b1573fe0}, isbn = {978-1-5090-4940-0}, keywords = {dblp}, pages = {200-201}, publisher = {IEEE}, timestamp = {2018-03-15T11:37:50.000+0100}, title = {A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2018.html#ClintonSTZSC18}, year = 2018 }