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Disambiguation of "Clinton, Michael"

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A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.

, , , , , and . ISSCC, page 200-201. IEEE, (2018)

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Clinton Givens

Clinton Enoch

Clinton Burford

William Clinton Maxwell

Jan Clinton Moritz Luedtke

 

Other publications of authors with the same name

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications., , , , , and . IEEE J. Solid State Circuits, 49 (1): 95-106 (2014)An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions., , , , , and . ISSCC, page 432-433. IEEE, (2013)Session 18 overview: Advanced embedded SRAM., and . ISSCC, page 314-315. IEEE, (2013)A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications., , , , , and . ISSCC, page 200-201. IEEE, (2018)Design and technology interaction beyond 32nm., , , , and . CICC, page 1-9. IEEE, (2011)12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications., , , , , , , , , and 4 other author(s). ISSCC, page 210-211. IEEE, (2017)Solutions for logic and processor core design at the 45nm technology node & and below., , , and . ICECS, page 923-926. IEEE, (2007)A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS., , , and . ISSCC, page 208-210. IEEE, (2011)Session 13 overview: High-performance embedded SRAM: Memory subcommittee., and . ISSCC, page 228-229. IEEE, (2012)