%0 Conference Paper %1 conf/lascas/ValdesPMRR16 %A Valdes, Andres M. A. %A Possani, Vinicius Neves %A Marranghello, Felipe S. %A Reis, André Inácio %A Ribas, Renato P. %B LASCAS %D 2016 %I IEEE %K dblp %P 227-230 %T Performance evaluation of optimized transistor networks built using independent-gate FinFET. %U http://dblp.uni-trier.de/db/conf/lascas/lascas2016.html#ValdesPMRR16 %@ 978-1-4673-7835-2

@inproceedings{conf/lascas/ValdesPMRR16, added-at = {2017-05-25T00:00:00.000+0200}, author = {Valdes, Andres M. A. and Possani, Vinicius Neves and Marranghello, Felipe S. and Reis, André Inácio and Ribas, Renato P.}, biburl = {https://www.bibsonomy.org/bibtex/29c5b3049e25e5a6567b2596e64890e60/dblp}, booktitle = {LASCAS}, crossref = {conf/lascas/2016}, ee = {https://doi.org/10.1109/LASCAS.2016.7451051}, interhash = {457905b0ecc95ae0bbddb9e00f9171b7}, intrahash = {9c5b3049e25e5a6567b2596e64890e60}, isbn = {978-1-4673-7835-2}, keywords = {dblp}, pages = {227-230}, publisher = {IEEE}, timestamp = {2019-10-17T19:47:37.000+0200}, title = {Performance evaluation of optimized transistor networks built using independent-gate FinFET.}, url = {http://dblp.uni-trier.de/db/conf/lascas/lascas2016.html#ValdesPMRR16}, year = 2016 }