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Performance evaluation of optimized transistor networks built using independent-gate FinFET.

, , , , and . LASCAS, page 227-230. IEEE, (2016)

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SwitchCraft: a framework for transistor network design., , , , , and . SBCCI, page 49-53. ACM, (2010)KL-Cuts: A new approach for logic synthesis targeting multiple output blocks., , , and . DATE, page 777-782. IEEE Computer Society, (2010)Exact lower bound for the number of switches in series to implement a combinational logic cell., , , and . ICCD, page 357-362. IEEE Computer Society, (2005)Improvements on the detection of false paths by using unateness and satisfiability., , , and . SBCCI, page 192-197. ACM, (2010)Area impact analysis of via-configurable regular fabric for digital integrated circuit design., , , , , and . SBCCI, page 103-108. ACM, (2011)Logic synthesis for manufacturability considering regularity and lithography printability., , , , , and . ISVLSI, page 230-235. IEEE Computer Socity, (2013)On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design., , , , , and . LATS, page 135-140. IEEE, (2016)Impact and optimization of lithography-aware regular layout in digital circuit design., , , , and . ICCD, page 279-284. IEEE Computer Society, (2011)Switch level optimization of digital CMOS gate networks., , , and . ISQED, page 324-329. IEEE Computer Society, (2009)ATMR design by construction based on two-level ALS., , , , and . SBCCI, page 1-6. IEEE, (2023)