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Disambiguation of "Marranghello, Felipe S."

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Performance evaluation of optimized transistor networks built using independent-gate FinFET.

, , , , and . LASCAS, page 227-230. IEEE, (2016)

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Felipe Zambaldi

Felipe Ortuño

Felipe Vieira

Felipe Huici

Felipe Herrera

 

Other publications of authors with the same name

Improved logic synthesis for memristive stateful logic using multi-memristor implication., , , , and . ISCAS, page 181-184. IEEE, (2015)Transistor sizing in lithography-aware regular fabrics., , , , and . SBCCI, page 97-102. ACM, (2011)Delay model for static CMOS complex gates., , and . SBCCI, page 1-6. IEEE, (2013)One-Sided Countermeasures for Side-Channel Attacks Can Backfire., , , and . WISEC, page 299-301. ACM, (2018)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , and . LASCAS, page 227-230. IEEE, (2016)Impact and optimization of lithography-aware regular layout in digital circuit design., , , , and . ICCD, page 279-284. IEEE Computer Society, (2011)CMOS inverter delay model based on DC transfer curve for slow input., , and . ISQED, page 651-657. IEEE, (2013)Design-oriented delay model for CMOS inverter., , and . SBCCI, page 1-6. IEEE, (2012)Binary adder circuit design using emerging MIGFET devices., , , , , and . ISQED, page 125-130. IEEE, (2017)LUT-Based Optimization For ASIC Design Flow., , , , , , , , and . DAC, page 871-876. IEEE, (2021)