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Delay model for static CMOS complex gates., , и . SBCCI, стр. 1-6. IEEE, (2013)Improved logic synthesis for memristive stateful logic using multi-memristor implication., , , , и . ISCAS, стр. 181-184. IEEE, (2015)Transistor sizing in lithography-aware regular fabrics., , , , и . SBCCI, стр. 97-102. ACM, (2011)Binary adder circuit design using emerging MIGFET devices., , , , , и . ISQED, стр. 125-130. IEEE, (2017)Design-oriented delay model for CMOS inverter., , и . SBCCI, стр. 1-6. IEEE, (2012)CMOS inverter delay model based on DC transfer curve for slow input., , и . ISQED, стр. 651-657. IEEE, (2013)LUT-Based Optimization For ASIC Design Flow., , , , , , , , и . DAC, стр. 871-876. IEEE, (2021)One-Sided Countermeasures for Side-Channel Attacks Can Backfire., , , и . WISEC, стр. 299-301. ACM, (2018)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , и . LASCAS, стр. 227-230. IEEE, (2016)SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC., , , и . IEEE Trans. Emerg. Top. Comput., 5 (2): 247-259 (2017)