%0 Journal Article %1 journals/dt/NetoPMMGRR20 %A Neto, Walter Lau %A Possani, Vinicius N. %A Marranghello, Felipe S. %A Matos, Jody Maick %A Gaillardon, Pierre-Emmanuel %A Reis, André Inácio %A Ribas, Renato Perez %D 2020 %J IEEE Des. Test %K dblp %N 3 %P 51-58 %T Exact Benchmark Circuits for Logic Synthesis. %U http://dblp.uni-trier.de/db/journals/dt/dt37.html#NetoPMMGRR20 %V 37

@article{journals/dt/NetoPMMGRR20, added-at = {2020-07-15T00:00:00.000+0200}, author = {Neto, Walter Lau and Possani, Vinicius N. and Marranghello, Felipe S. and Matos, Jody Maick and Gaillardon, Pierre-Emmanuel and Reis, André Inácio and Ribas, Renato Perez}, biburl = {https://www.bibsonomy.org/bibtex/239cce5236efe1cd17116ba1ea52a8c8b/dblp}, ee = {https://doi.org/10.1109/MDAT.2019.2952348}, interhash = {51c27023ee0ad0ca2fbcb9db190f81e8}, intrahash = {39cce5236efe1cd17116ba1ea52a8c8b}, journal = {IEEE Des. Test}, keywords = {dblp}, number = 3, pages = {51-58}, timestamp = {2020-07-24T00:37:38.000+0200}, title = {Exact Benchmark Circuits for Logic Synthesis.}, url = {http://dblp.uni-trier.de/db/journals/dt/dt37.html#NetoPMMGRR20}, volume = 37, year = 2020 }