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Disambiguation of "Possani, Vinicius N."

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Exact Benchmark Circuits for Logic Synthesis.

, , , , , , and . IEEE Des. Test, 37 (3): 51-58 (2020)

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Vinícius Liebel

Vinícius Maran

Vinicius Malatesta

Vinicius Mariano Carvalho

 

Other publications of authors with the same name

Transistor Count Optimization in IG FinFET Network Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)Exact Benchmark Circuits for Logic Synthesis., , , , , , and . IEEE Des. Test, 37 (3): 51-58 (2020)Unlocking fine-grain parallelism for AIG rewriting., , , , , and . ICCAD, page 87. ACM, (2018)NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2012)Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation., , , , , and . SBCCI, page 1-6. IEEE, (2018)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , and . DAC, page 1-6. IEEE, (2020)Majority-based Design Flow for AQFP Superconducting Family., , , , , , , , , and 1 other author(s). DATE, page 34-39. IEEE, (2022)Transistor-level optimization of CMOS complex gates., , , , , and . LASCAS, page 1-4. IEEE, (2013)LUT-Based Optimization For ASIC Design Flow., , , , , , , , and . DAC, page 871-876. IEEE, (2021)Exploring Independent Gates in FinFET-Based Transistor Network Generation., , , , and . SBCCI, page 41:1-41:6. ACM, (2014)