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Exact Benchmark Circuits for Logic Synthesis.

W. Neto, V. Possani, F. Marranghello, J. Matos, P. Gaillardon, A. Reis, and R. Ribas. IEEE Des. Test, 37 (3): 51-58 (2020)

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Oswaldo Cavalcanti Costa Lima Neto

António Manuel Martins Neto

Arthur Ayres Neto

João Pacheco Fernandes Neto

Manoel Marcos Freire d'Aguiar Neto

Other publications of authors with the same name

A Scalable Mixed Synthesis Framework for Heterogeneous Networks.M. Austin, S. Temple, W. Neto, L. Amarù, X. Tang, and P. Gaillardon. DATE, page 670-673. IEEE, (2020)Exact Benchmark Circuits for Logic Synthesis.W. Neto, V. Possani, F. Marranghello, J. Matos, P. Gaillardon, A. Reis, and R. Ribas. IEEE Des. Test, 37 (3): 51-58 (2020)Improving LUT-based optimization for ASICs.W. Neto, L. Amarù, V. Possani, P. Vuillod, J. Luo, A. Mishchenko, and P. Gaillardon. DAC, page 421-426. ACM, (2022)Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.S. Rai, W. Neto, Y. Miyasaka, X. Zhang, M. Yu, Q. Yi, M. Fujita, G. Manske, M. Pontes, L. da Rosa Jr. and 31 other author(s). CoRR, (2020)Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis.S. Temple, W. Neto, A. Snelgrove, X. Tang, and P. Gaillardon. DAC, page 1331-1334. IEEE, (2021)Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.W. Neto, V. Possani, F. Marranghello, J. Matos, A. Reis, and R. Ribas. SBCCI, page 1-6. IEEE, (2018)A standard cell characterization flow for non-standard voltage supplies.M. Gibiluka, M. Moreira, W. Neto, and N. Calazans. SBCCI, page 1-6. IEEE, (2016)Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.W. Neto, X. Tang, M. Austin, L. Amarù, and P. Gaillardon. ISVLSI, page 224-229. IEEE, (2019)LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.W. Neto, M. Austin, S. Temple, L. Amarù, X. Tang, and P. Gaillardon. ICCAD, page 1-6. ACM, (2019)Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization.W. Neto, M. Moreira, L. Amarù, C. Yu, and P. Gaillardon. ASP-DAC, page 530-535. ACM, (2021)

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Disambiguation of "Neto, Walter Lau"

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Exact Benchmark Circuits for Logic Synthesis.

Please choose a person to relate this publication to

Oswaldo Cavalcanti Costa Lima Neto

António Manuel Martins Neto

Arthur Ayres Neto

João Pacheco Fernandes Neto

Manoel Marcos Freire d'Aguiar Neto

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Neto, Walter Lau"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Exact Benchmark Circuits for Logic Synthesis.

Please choose a person to relate this publication to

Oswaldo Cavalcanti Costa Lima Neto

António Manuel Martins Neto

Arthur Ayres Neto

João Pacheco Fernandes Neto

Manoel Marcos Freire d'Aguiar Neto

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Exact Benchmark Circuits for Logic Synthesis.