%0 Journal Article %1 journals/tcsv/ChengHCLC07 %A Cheng, Chih-Chi %A Huang, Chao-Tsung %A Chen, Ching-Yeh %A Lian, Chung-Jr %A Chen, Liang-Gee %D 2007 %J IEEE Trans. Circuits Syst. Video Techn. %K dblp %N 7 %P 814-822 %T On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform. %U http://dblp.uni-trier.de/db/journals/tcsv/tcsv17.html#ChengHCLC07 %V 17

@article{journals/tcsv/ChengHCLC07, added-at = {2016-03-18T00:00:00.000+0100}, author = {Cheng, Chih-Chi and Huang, Chao-Tsung and Chen, Ching-Yeh and Lian, Chung-Jr and Chen, Liang-Gee}, biburl = {https://www.bibsonomy.org/bibtex/2cf5a776e45c86a3280510e52480703b8/dblp}, ee = {http://dx.doi.org/10.1109/TCSVT.2007.897106}, interhash = {627c8bb2d1866af5feb3e465f04c5c7a}, intrahash = {cf5a776e45c86a3280510e52480703b8}, journal = {IEEE Trans. Circuits Syst. Video Techn.}, keywords = {dblp}, number = 7, pages = {814-822}, timestamp = {2016-03-19T11:38:00.000+0100}, title = {On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.}, url = {http://dblp.uni-trier.de/db/journals/tcsv/tcsv17.html#ChengHCLC07}, volume = 17, year = 2007 }