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On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.

C. Cheng, C. Huang, C. Chen, C. Lian, and L. Chen. IEEE Trans. Circuits Syst. Video Techn., 17 (7): 814-822 (2007)

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Walid Shehab Chihab

Matei Chihaia

Cristian IonutÌ§ Chihaia

Houssem-Eddine Chihoub

Ping-I Chih

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iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.C. Cheng, C. Lin, C. Li, S. Chang, and L. Chen. DAC, page 90-95. ACM, (2008)Application Layer Error Correction Scheme for Video Header Protection on Wireless Network.C. Pan, I. Lee, S. Huang, C. Cheng, C. Lian, and L. Chen. ISM, page 499-505. IEEE Computer Society, (2005)Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.Y. Chen, C. Chen, C. Cheng, and L. Chen. ICME, page 365-368. IEEE Computer Society, (2006)Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture.Y. Chang, C. Cheng, C. Chen, H. Fang, and L. Chen. SiPS, page 428-433. IEEE, (2006)On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.C. Cheng, C. Huang, C. Chen, C. Lian, and L. Chen. IEEE Trans. Circuits Syst. Video Techn., 17 (7): 814-822 (2007)Diastolic arrays: throughput-driven reconfigurable computing.M. Cho, C. Cheng, M. Kinsy, G. Suh, and S. Devadas. ICCAD, page 457-464. IEEE Computer Society, (2008)Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.Y. Chen, C. Cheng, T. Chuang, C. Chen, S. Chien, and L. Chen. IEEE Trans. Circuits Syst. Video Techn., 18 (1): 98-109 (2008)Memory efficient JPEG2000 architecture with stripe pipeline scheme.H. Fang, Y. Chang, C. Cheng, C. Chen, and L. Chen. ICASSP (5), page 1-4. IEEE, (2005)Line Buffer Wordlength Analysis for Line-Based 2-D DWT.C. Cheng, C. Huang, J. Chang, and L. Chen. ICASSP (3), page 924-927. IEEE, (2006)Frame-level data reuse for motion-compensated temporal filtering.C. Chen, Y. Chen, C. Cheng, and L. Chen. ISCAS, IEEE, (2006)

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Disambiguation of "Cheng, Chih-Chi"

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On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.

Please choose a person to relate this publication to

Walid Shehab Chihab

Matei Chihaia

Cristian IonutÌ§ Chihaia

Houssem-Eddine Chihoub

Ping-I Chih

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cheng, Chih-Chi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.

Please choose a person to relate this publication to

Walid Shehab Chihab

Matei Chihaia

Cristian IonutÌ§ Chihaia

Houssem-Eddine Chihoub

Ping-I Chih

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MSOffice XML

On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.