%0 Conference Paper %1 conf/essderc/TanakaIS15 %A Tanaka, Chika %A Ikeda, Keiji %A Saitoh, Masumi %B ESSDERC %D 2015 %I IEEE %K dblp %P 258-261 %T New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. %U http://dblp.uni-trier.de/db/conf/essderc/essderc2015.html#TanakaIS15 %@ 978-1-4673-7135-3

@inproceedings{conf/essderc/TanakaIS15, added-at = {2017-05-19T00:00:00.000+0200}, author = {Tanaka, Chika and Ikeda, Keiji and Saitoh, Masumi}, biburl = {https://www.bibsonomy.org/bibtex/2c98b37b920d5574219c9770be89a6960/dblp}, booktitle = {ESSDERC}, crossref = {conf/essderc/2015}, ee = {https://doi.org/10.1109/ESSDERC.2015.7324763}, interhash = {6342ae89f59471931c9945fefbfe0b20}, intrahash = {c98b37b920d5574219c9770be89a6960}, isbn = {978-1-4673-7135-3}, keywords = {dblp}, pages = {258-261}, publisher = {IEEE}, timestamp = {2019-10-17T12:39:51.000+0200}, title = {New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering.}, url = {http://dblp.uni-trier.de/db/conf/essderc/essderc2015.html#TanakaIS15}, year = 2015 }