%0 Conference Paper %1 conf/vlsic/SunB0HP020 %A Sun, Xun %A Boora, Akshat %A Pamula, Rajesh %A Huang, Chi-Hsiang %A Peña-Colaiocco, Diego %A Sathe, Visvesh S. %B VLSI Circuits %D 2020 %I IEEE %K dblp %P 1-2 %T UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2020.html#SunB0HP020 %@ 978-1-7281-9942-9

@inproceedings{conf/vlsic/SunB0HP020, added-at = {2020-10-29T00:00:00.000+0100}, author = {Sun, Xun and Boora, Akshat and Pamula, Rajesh and Huang, Chi-Hsiang and Peña-Colaiocco, Diego and Sathe, Visvesh S.}, biburl = {https://www.bibsonomy.org/bibtex/25e745cdcdf8e2886d6fd4d3b6d434e4d/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2020}, ee = {https://doi.org/10.1109/VLSICircuits18222.2020.9162982}, interhash = {6b8ef88213a102e7a8e2811bc34bc7b1}, intrahash = {5e745cdcdf8e2886d6fd4d3b6d434e4d}, isbn = {978-1-7281-9942-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2020-10-30T11:35:18.000+0100}, title = {UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2020.html#SunB0HP020}, year = 2020 }