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Disambiguation of "Huang, Chi-Hsiang"

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UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)

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Hsiang-Huang Wu

Chu-Hsiang Huang

Li-Chi Huang

Hsiang Kuang

Hsiang-Shang Ko

 

Other publications of authors with the same name

An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS., , , , and . ISSCC, page 1-3. IEEE, (2022)Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains., , , , and . IEEE J. Solid State Circuits, 58 (1): 68-77 (2023)Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter., , and . IEEE J. Solid State Circuits, 53 (2): 596-604 (2018)A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS., , , , , and . ISSCC, page 416-418. IEEE, (2021)Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains., , , , and . ISSCC, page 222-224. IEEE, (2022)Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)An Evolutionary Approach to Finding Schemas for 3-Class Protein Secondary Structure Prediction.. CSB, page 488-491. IEEE Computer Society, (2003)