%0 Conference Paper %1 conf/vlsit/KellerVDTZDGK22 %A Keller, Ben %A Venkatesan, Rangharajan %A Dai, Steve %A Tell, Stephen G. %A Zimmer, Brian %A Dally, William J. %A Gray, C. Thomas %A Khailany, Brucek %B VLSI Technology and Circuits %D 2022 %I IEEE %K dblp %P 16-17 %T A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#KellerVDTZDGK22 %@ 978-1-6654-9772-5

@inproceedings{conf/vlsit/KellerVDTZDGK22, added-at = {2022-08-04T00:00:00.000+0200}, author = {Keller, Ben and Venkatesan, Rangharajan and Dai, Steve and Tell, Stephen G. and Zimmer, Brian and Dally, William J. and Gray, C. Thomas and Khailany, Brucek}, biburl = {https://www.bibsonomy.org/bibtex/22df26de4f9fa311a129c4b067756b433/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2022}, ee = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830277}, interhash = {6ca4b01923c37b8c2b4626fc6713cad3}, intrahash = {2df26de4f9fa311a129c4b067756b433}, isbn = {978-1-6654-9772-5}, keywords = {dblp}, pages = {16-17}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:06.000+0200}, title = {A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#KellerVDTZDGK22}, year = 2022 }