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Disambiguation of "Keller, Ben"

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A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm.

, , , , , , , and . VLSI Technology and Circuits, page 16-17. IEEE, (2022)

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Ben Schmehe

Ben Schöttker

Ben Novak

Ben Schacher

Ben Schloesser

 

Other publications of authors with the same name

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (4): 920-932 (2020)Accelerating Chip Design With Machine Learning., , , , , , , , , and 1 other author(s). IEEE Micro, 40 (6): 23-32 (2020)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET., , , , , , , , , and . ASYNC, page 27-35. IEEE, (2019)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)A Pausible Bisynchronous FIFO for GALS Systems., , and . ASYNC, page 1-8. IEEE Computer Society, (2015)A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm., , , , , , , , , and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)MAGNet: A Modular Accelerator Generator for Neural Networks., , , , , , , , , and 6 other author(s). ICCAD, page 1-8. ACM, (2019)MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification., , , , , and . DATE, page 1825-1828. IEEE, (2021)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI., , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)