%0 Conference Paper %1 conf/isscc/ChangWKSLYKLC12 %A Chang, Meng-Fan %A Wu, Che-Wei %A Kuo, Chia-Chen %A Shen, Shin-Jang %A Lin, Ku-Feng %A Yang, Shu-Meng %A King, Ya-Chin %A Lin, Chorng-Jung %A Chih, Yu-Der %B ISSCC %D 2012 %I IEEE %K dblp %P 434-436 %T A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2012.html#ChangWKSLYKLC12 %@ 978-1-4673-0376-7

@inproceedings{conf/isscc/ChangWKSLYKLC12, added-at = {2012-04-18T00:00:00.000+0200}, author = {Chang, Meng-Fan and Wu, Che-Wei and Kuo, Chia-Chen and Shen, Shin-Jang and Lin, Ku-Feng and Yang, Shu-Meng and King, Ya-Chin and Lin, Chorng-Jung and Chih, Yu-Der}, biburl = {https://www.bibsonomy.org/bibtex/2b95e4f4b36cef80e4673dcfad4cb0e4e/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2012}, ee = {http://dx.doi.org/10.1109/ISSCC.2012.6177079}, interhash = {868452b4d8936c86842aafe1376c6721}, intrahash = {b95e4f4b36cef80e4673dcfad4cb0e4e}, isbn = {978-1-4673-0376-7}, keywords = {dblp}, pages = {434-436}, publisher = {IEEE}, timestamp = {2012-04-19T11:43:31.000+0200}, title = {A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2012.html#ChangWKSLYKLC12}, year = 2012 }