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A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.

M. Chang, C. Wu, C. Kuo, S. Shen, K. Lin, S. Yang, Y. King, C. Lin, и Y. Chih. ISSCC, стр. 434-436. IEEE, (2012)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matchingM. Zhang. TU München, (2009)

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17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.M. Chang, C. Lin, A. Lee, C. Kuo, G. Yang, H. Tsai, T. Chen, S. Sheu, P. Tseng, H. Lee и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification.T. Hsu, G. Chen, Y. Chen, R. Liu, C. Lo, K. Tang, M. Chang, и C. Hsieh. IEEE J. Solid State Circuits, 58 (11): 3266-3274 (ноября 2023)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.A. Lele, M. Chang, S. Spetalnick, B. Crafton, S. Konno, Z. Wan, A. Bhat, W. Khwa, Y. Chih, M. Chang и 1 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 52-64 (января 2024)A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.H. Hsu, T. Wen, W. Huang, W. Khwa, Y. Lo, C. Jhang, Y. Chin, Y. Chen, C. Lo, R. Liu и 5 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 116-127 (января 2024)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.A. Lee, C. Lo, C. Lin, W. Chen, K. Hsu, Z. Wang, F. Su, Z. Yuan, Q. Wei, Y. King и 8 other автор(ы). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.Z. Wang, Y. Liu, A. Lee, F. Su, C. Lo, Z. Yuan, J. Li, C. Lin, W. Chen, H. Chiu и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang и 7 other автор(ы). ISSCC, стр. 494-496. IEEE, (2018)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache.K. Yang, H. Tsai, C. Li, P. Jendra, M. Chang, и T. Chen. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications.W. Khwa, M. Chang, J. Wu, M. Lee, T. Su, K. Yang, T. Chen, T. Wang, H. Li, M. BrightSky и 3 other автор(ы). IEEE J. Solid State Circuits, 52 (1): 218-228 (2017)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.M. Chang, M. Chen, L. Chen, S. Yang, Y. Kuo, J. Wu, H. Su, Y. Chu, W. Wu, T. Yang и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)

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