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A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.

M. Chang, C. Wu, C. Kuo, S. Shen, K. Lin, S. Yang, Y. King, C. Lin, and Y. Chih. ISSCC, page 434-436. IEEE, (2012)

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Feng Lin

Ku-Yen Lin

Lin Lin

Other publications of authors with the same name

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.M. Chang, S. Sheu, K. Lin, C. Wu, C. Kuo, P. Chiu, Y. Yang, Y. Chen, H. Lee, C. Lien and 5 other author(s). IEEE J. Solid State Circuits, 48 (3): 878-891 (2013)A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.S. Sheu, M. Chang, K. Lin, C. Wu, Y. Chen, P. Chiu, C. Kuo, Y. Yang, P. Chiang, W. Lin and 12 other author(s). ISSCC, page 200-202. IEEE, (2011)Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.Y. Shih, C. Lee, Y. Chang, P. Lee, H. Lin, Y. Chen, K. Lin, T. Yeh, H. Yu, H. Chuang and 2 other author(s). VLSI Circuits, page 79-80. IEEE, (2018)A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications.M. Chang, S. Yang, C. Liang, C. Chiang, P. Chiu, K. Lin, Y. Chu, W. Wu, and H. Yamauchi. ISSCC, page 266-267. IEEE, (2010)Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology.H. Yu, K. Lin, K. Lin, C. Huang, Y. Chih, T. Ong, T. Chang, S. Natarajan, and L. Tran. ISSCC, page 224-225. IEEE, (2013)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements.M. Chang, S. Yang, C. Liang, C. Chiang, P. Chiu, and K. Lin. IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V.H. Yu, K. Lin, K. Lin, Y. Chih, and S. Natarajan. VLSI-DAT, page 1-4. IEEE, (2013)19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme.M. Chang, J. Wu, T. Chien, Y. Liu, T. Yang, W. Shen, Y. King, C. Lin, K. Lin, Y. Chih and 2 other author(s). ISSCC, page 332-333. IEEE, (2014)15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes.K. Lin, H. Noguchi, Y. Shih, P. Yuh, Y. Lee, T. Chang, S. Huang, Y. Lin, C. Lee, Y. Huang and 16 other author(s). ISSCC, page 292-294. IEEE, (2024)Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.M. Chang, J. Wu, T. Chien, Y. Liu, T. Yang, W. Shen, Y. King, C. Lin, K. Lin, Y. Chih and 1 other author(s). IEEE J. Solid State Circuits, 50 (11): 2786-2795 (2015)

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Disambiguation of "Lin, Ku-Feng"

Please choose a person to relate this publication to

Feng Lin

Feng Lin

Ku-Yen Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Ku-Feng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.

Please choose a person to relate this publication to

Feng Lin

Feng Lin

Ku-Yen Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation