%0 Conference Paper %1 conf/dac/ZhengWFYCHCYL20 %A Zheng, Qilin %A Wang, Zongwei %A Feng, Zishun %A Yan, Bonan %A Cai, Yimao %A Huang, Ru %A Chen, Yiran %A Yang, Chia-Lin %A Li, Hai Helen %B DAC %D 2020 %I IEEE %K dblp %P 1-6 %T Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. %U http://dblp.uni-trier.de/db/conf/dac/dac2020.html#ZhengWFYCHCYL20 %@ 978-1-7281-1085-1

@inproceedings{conf/dac/ZhengWFYCHCYL20, added-at = {2024-06-04T00:00:00.000+0200}, author = {Zheng, Qilin and Wang, Zongwei and Feng, Zishun and Yan, Bonan and Cai, Yimao and Huang, Ru and Chen, Yiran and Yang, Chia-Lin and Li, Hai Helen}, biburl = {https://www.bibsonomy.org/bibtex/2c9d98fba2c5f0a66f9e24f68b5fb0781/dblp}, booktitle = {DAC}, crossref = {conf/dac/2020}, ee = {https://doi.org/10.1109/DAC18072.2020.9218590}, interhash = {9735d8639482a78c8156c2e302572f85}, intrahash = {c9d98fba2c5f0a66f9e24f68b5fb0781}, isbn = {978-1-7281-1085-1}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2024-06-10T07:18:47.000+0200}, title = {Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2020.html#ZhengWFYCHCYL20}, year = 2020 }