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Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.

Q. Zheng, Z. Wang, Z. Feng, B. Yan, Y. Cai, R. Huang, Y. Chen, C. Yang, and H. Li. DAC, page 1-6. IEEE, (2020)

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Jian Cai

Yongjie Cai

Lijun Cai

Cai Berg

Lu Cai

Other publications of authors with the same name

A 3D multi-layer CMOS-RRAM accelerator for neural network.H. Huang, L. Ni, Y. Wang, H. Yu, Z. Wang, Y. Cai, and R. Huang. 3DIC, page 1-5. IEEE, (2016)A High-Throughput and Configurable TRNG Based on Dual-Mode Memristor for Stochastic Computing.Z. Cheng, Y. Qin, Z. Wang, F. Zou, C. Wang, Y. Cai, and R. Huang. ICTA, page 108-109. IEEE, (2023)ASAP: An Efficient and Reliable Programming Algorithm for Multi-level RRAM Cell.J. Sun, Z. Wang, J. Gao, L. Shan, Q. Wang, Y. Yang, Y. Cai, and R. Huang. IRPS, page 1-4. IEEE, (2024)An electronic synapse based on tantalum oxide material.X. Yang, Y. Cai, Z. Zhang, M. Yu, and R. Huang. NVMTS, page 1-4. IEEE, (2015)Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing.J. Li, Z. Wang, C. Wang, Y. Cai, and R. Huang. ICTA, page 144-145. IEEE, (2023)Rotational Pattern Recognition by Spiking Correlated Neural Network Based on Dual-Gated MoS 2 Neuristor.L. Bao, Z. Wang, Z. Yu, Y. Ling, Y. Cai, and R. Huang. Adv. Intell. Syst., 2 (11): 2000102 (2020)Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.Q. Zheng, Z. Wang, J. Kang, Z. Yu, Y. Cai, and J. Xu. NVMTS, page 1-3. IEEE, (2018)Enhancement of HfO2 Based RRAM Performance Through Hexagonal Boron Nitride Interface Layer.Y. Chen, Z. Wang, Z. Zhang, L. Wang, Y. Fang, J. Lou, K. Liu, J. Xu, Y. Cai, and R. Huang. NVMTS, page 1-3. IEEE, (2018)Resistive switching in organic memory devices for flexible applications.R. Huang, Y. Cai, Y. Liu, W. Bai, Y. Kuang, and Y. Wang. ISCAS, page 838-841. IEEE, (2014)Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.Q. Zheng, Z. Wang, Z. Feng, B. Yan, Y. Cai, R. Huang, Y. Chen, C. Yang, and H. Li. DAC, page 1-6. IEEE, (2020)

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Disambiguation of "Cai, Yimao"

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Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.

Please choose a person to relate this publication to

Jian Cai

Yongjie Cai

Lijun Cai

Cai Berg

Lu Cai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cai, Yimao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.

Please choose a person to relate this publication to

Jian Cai

Yongjie Cai

Lijun Cai

Cai Berg

Lu Cai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.