%0 Conference Paper %1 conf/vlsit/JiangLHY22 %A Jiang, Hongwu %A Li, Wantong %A Huang, Shanshi %A Yu, Shimeng %B VLSI Technology and Circuits %D 2022 %I IEEE %K dblp %P 266-267 %T A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#JiangLHY22 %@ 978-1-6654-9772-5

@inproceedings{conf/vlsit/JiangLHY22, added-at = {2023-03-21T00:00:00.000+0100}, author = {Jiang, Hongwu and Li, Wantong and Huang, Shanshi and Yu, Shimeng}, biburl = {https://www.bibsonomy.org/bibtex/270ae8a34a64a3e10437ba9125e3225fe/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2022}, ee = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830211}, interhash = {a1e2f9cad41a3a56f3f060f2e87495f3}, intrahash = {70ae8a34a64a3e10437ba9125e3225fe}, isbn = {978-1-6654-9772-5}, keywords = {dblp}, pages = {266-267}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:06.000+0200}, title = {A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#JiangLHY22}, year = 2022 }