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Disambiguation of "Huang, Shanshi"

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A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.

, , , and . VLSI Technology and Circuits, page 266-267. IEEE, (2022)

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Josef Huang

Pa Huang

Zheng Huang

Yuejun Huang

Shiwei Huang

 

Other publications of authors with the same name

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training., , , , and . CoRR, (2020)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2306-2319 (2021)A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference., , , , and . ACM Trans. Design Autom. Electr. Syst., 26 (6): 45:1-45:18 (2021)Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune., , and . NVMSA, page 1-6. IEEE, (2021)A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training., , , , , , , , , and . DAC, page 1-6. IEEE, (2020)Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects., , , and . CICC, page 1-4. IEEE, (2020)A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References., , , , and . ESSCIRC, page 79-82. IEEE, (2021)Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security., , , , and . CICC, page 1-2. IEEE, (2021)MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture., , , and . ISCAS, page 1-5. IEEE, (2020)Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning., , , , and . ISCAS, page 1-5. IEEE, (2021)