Article,
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak, J. Setter, J. Thomas, K. Sreedhar, P. Chen, N. Bhagdikar, Z. Myers, B. D'Agostino, P. Joshi, S. Richardson, C. Torng, M. Horowitz, and P. Raina.IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)
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- IEEE J. Solid State Circuits
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- 3
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- 947-959
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- https://doi.org/10.1109/JSSC.2023.3313116
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%1 journals/jssc/FengKKMCLNSZNSTSCBMDJRTHR24
%A Feng, Kathleen
%A Kong, Taeyoung
%A Koul, Kalhan
%A Melchert, Jackson
%A Carsello, Alex
%A Liu, Qiaoyi
%A Nyengele, Gedeon
%A Strange, Maxwell
%A Zhang, Keyi
%A Nayak, Ankita
%A Setter, Jeff
%A Thomas, James
%A Sreedhar, Kavya
%A Chen, Po-Han
%A Bhagdikar, Nikhil
%A Myers, Zachary
%A D'Agostino, Brandon
%A Joshi, Pranil
%A Richardson, Stephen
%A Torng, Christopher
%A Horowitz, Mark
%A Raina, Priyanka
%D 2024
%J IEEE J. Solid State Circuits
%K dblp
%N 3
%P 947-959
%T Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc59.html#FengKKMCLNSZNSTSCBMDJRTHR24
%V 59
@article{journals/jssc/FengKKMCLNSZNSTSCBMDJRTHR24,
added-at = {2024-03-16T00:00:00.000+0100},
author = {Feng, Kathleen and Kong, Taeyoung and Koul, Kalhan and Melchert, Jackson and Carsello, Alex and Liu, Qiaoyi and Nyengele, Gedeon and Strange, Maxwell and Zhang, Keyi and Nayak, Ankita and Setter, Jeff and Thomas, James and Sreedhar, Kavya and Chen, Po-Han and Bhagdikar, Nikhil and Myers, Zachary and D'Agostino, Brandon and Joshi, Pranil and Richardson, Stephen and Torng, Christopher and Horowitz, Mark and Raina, Priyanka},
biburl = {https://www.bibsonomy.org/bibtex/26d30431acff8bd1d84dae741b12c3800/dblp},
ee = {https://doi.org/10.1109/JSSC.2023.3313116},
interhash = {d8d776c1447953fac242a132065a14da},
intrahash = {6d30431acff8bd1d84dae741b12c3800},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
month = {March},
number = 3,
pages = {947-959},
timestamp = {2024-04-08T10:44:38.000+0200},
title = {Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc59.html#FengKKMCLNSZNSTSCBMDJRTHR24},
volume = 59,
year = 2024
}