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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak, J. Setter, J. Thomas, K. Sreedhar, P. Chen, N. Bhagdikar, Z. Myers, B. D'Agostino, P. Joshi, S. Richardson, C. Torng, M. Horowitz, and P. Raina. IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)

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Helen Jackson

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Peter Jackson

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Synthesizing Instruction Selection Rewrite Rules from RTL using SMT.R. Daly, C. Donovick, J. Melchert, R. Setaluri, N. Tsiskaridze, P. Raina, C. Barrett, and P. Hanrahan. FMCAD, page 139-150. IEEE, (2022)APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis.J. Melchert, K. Feng, C. Donovick, R. Daly, R. Sharma, C. Barrett, M. Horowitz, P. Hanrahan, and P. Raina. ASPLOS (3), page 33-45. ACM, (2023)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.A. Carsello, K. Feng, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)A Comparative Study of Local Net Modeling Using Machine Learning.J. Melchert, B. Zhang, and A. Davoodi. ACM Great Lakes Symposium on VLSI, page 273-278. ACM, (2018)Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.K. Feng, A. Carsello, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). HCS, page 1-30. IEEE, (2022)Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.J. Melchert, K. Zhang, Y. Mei, M. Horowitz, C. Torng, and P. Raina. IEEE Comput. Archit. Lett., 22 (1): 45-48 (January 2023)SAADI: a scalable accuracy approximate divider for dynamic energy-quality scaling.S. Behroozi, J. Li, J. Melchert, and Y. Kim. ASP-DAC, page 481-486. ACM, (2019)Creating an Agile Hardware Design Flow.R. Bahr, C. Barrett, N. Bhagdikar, A. Carsello, R. Daly, C. Donovick, D. Durst, K. Fatahalian, K. Feng, P. Hanrahan and 22 other author(s). DAC, page 1-6. IEEE, (2020)

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Disambiguation of "Melchert, Jackson"

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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Helen Jackson

Michelle Jackson

Peter Jackson

David Jackson

Jackson Francomme

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Melchert, Jackson"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Helen Jackson

Michelle Jackson

Peter Jackson

David Jackson

Jackson Francomme

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.