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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

, , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)

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Onyx: A Programmable Accelerator for Sparse Tensor Algebra., , , , , , , , , and 11 other author(s). HCS, page 1-91. IEEE, (2024)CaTDet: Cascaded Tracked Detector for Efficient Object Detection from Video., , and . CoRR, (2018)Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration., , , , , , , , , and 13 other author(s). HCS, page 1-30. IEEE, (2022)Creating an Agile Hardware Design Flow., , , , , , , , , and 22 other author(s). DAC, page 1-6. IEEE, (2020)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications., , , , , , , , , and 11 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays., , , , and . CoRR, (2023)CaTDet: Cascaded Tracked Detector for Efficient Object Detection from Video., , and . SysML, mlsys.org, (2019)