%0 Journal Article %1 journals/jssc/KurodaFMNYSSNMK96 %A Kuroda, Tadahiro %A Fujita, Tetsuya %A Mita, Shinji %A Nagamatsu, Tetsu %A Yoshioka, Shinichi %A Suzuki, Kojiro %A Sano, Fumihiko %A Norishima, Masayuki %A Murota, Masayuki %A Kako, Makoto %A Kinugawa, Masaaki %A Kakurnu, Masakazu %A Sakurai, Takayasu %D 1996 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1770-1779 %T A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. %U http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#KurodaFMNYSSNMK96 %V 31

@article{journals/jssc/KurodaFMNYSSNMK96, added-at = {2022-07-26T00:00:00.000+0200}, author = {Kuroda, Tadahiro and Fujita, Tetsuya and Mita, Shinji and Nagamatsu, Tetsu and Yoshioka, Shinichi and Suzuki, Kojiro and Sano, Fumihiko and Norishima, Masayuki and Murota, Masayuki and Kako, Makoto and Kinugawa, Masaaki and Kakurnu, Masakazu and Sakurai, Takayasu}, biburl = {https://www.bibsonomy.org/bibtex/2ebbfdf7fd79d40e864962cbf44a8685c/dblp}, ee = {https://doi.org/10.1109/JSSC.1996.542322}, interhash = {fcaaeb66f95d707eaf03b2e2cd38b6e0}, intrahash = {ebbfdf7fd79d40e864962cbf44a8685c}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1770-1779}, timestamp = {2024-04-08T10:44:35.000+0200}, title = {A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#KurodaFMNYSSNMK96}, volume = 31, year = 1996 }