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A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 31 (11): 1770-1779 (1996)

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A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 31 (11): 1770-1779 (1996)The Block Cipher Hierocrypt., , , and . Selected Areas in Cryptography, volume 2012 of Lecture Notes in Computer Science, page 72-88. Springer, (2000)A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)Performance Evaluation of AES Finalists on the High-End Smart Card., , , and . AES Candidate Conference, page 82-93. National Institute of Standards and Technology,, (2000)Cox-Rower Architecture for Fast Parallel Montgomery Multiplication., , , and . EUROCRYPT, volume 1807 of Lecture Notes in Computer Science, page 523-538. Springer, (2000)