%0 Journal Article %1 journals/tcad/ChenLZZLHYS24 %A Chen, Shixin %A Li, Shanyi %A Zhuang, Zhen %A Zheng, Su %A Liang, Zheng %A Ho, Tsung-Yi %A Yu, Bei %A Sangiovanni-Vincentelli, Alberto L. %D 2024 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 6 %P 1638-1649 %T Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration. %U http://dblp.uni-trier.de/db/journals/tcad/tcad43.html#ChenLZZLHYS24 %V 43

@article{journals/tcad/ChenLZZLHYS24, added-at = {2024-08-04T00:00:00.000+0200}, author = {Chen, Shixin and Li, Shanyi and Zhuang, Zhen and Zheng, Su and Liang, Zheng and Ho, Tsung-Yi and Yu, Bei and Sangiovanni-Vincentelli, Alberto L.}, biburl = {https://www.bibsonomy.org/bibtex/26ba62adcd08fccfb92c8cf841807ff98/dblp}, ee = {https://doi.org/10.1109/TCAD.2023.3347302}, interhash = {ff9e80f54cddd985787d0d801b904948}, intrahash = {6ba62adcd08fccfb92c8cf841807ff98}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, month = {June}, number = 6, pages = {1638-1649}, timestamp = {2024-08-05T07:10:55.000+0200}, title = {Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad43.html#ChenLZZLHYS24}, volume = 43, year = 2024 }