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Disambiguation of "Yu, Bei"

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Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (6): 1638-1649 (June 2024)

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Bei Yu

Bei-Bei Yang

Rongxing Bei

Bei Hu

Bei Cheng

 

Other publications of authors with the same name

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting., , and . CoRR, (2014)Methodology for standard cell compliance and detailed placement for triple patterning lithography., , , and . CoRR, (2014)Incremental Layer Assignment for Timing Optimization., , , and . ACM Trans. Design Autom. Electr. Syst., 22 (4): 75:1-75:25 (2017)Floorplanning and Topology Generation for Application-Specific Network-on-Chip., , , and . CoRR, (2014)Pushing multiple patterning in sub-10nm: are we ready?, , , , and . DAC, page 197:1-197:6. ACM, (2015)PARR: pin access planning and regular routing for self-aligned double patterning., , , , and . DAC, page 28:1-28:6. ACM, (2015)Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design., , , , , and . DAC, page 70:1-70:6. ACM, (2017)Toward Predicting Popularity of Social Marketing Messages., , and . SBP, volume 6589 of Lecture Notes in Computer Science, page 317-324. Springer, (2011)CAD Tool Design Space Exploration via Bayesian Optimization., , and . CoRR, (2019)Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1147-1160 (2019)