%0 Conference Paper %1 conf/vlsic/WangQDWCLLWY21 %A Wang, Yang %A Qin, Yubin %A Deng, Dazheng %A Wei, Jingchuan %A Chen, Tianbao %A Lin, Xinhan %A Liu, Leibo %A Wei, Shaojun %A Yin, Shouyi %B VLSI Circuits %D 2021 %I IEEE %K dblp %P 1-2 %T A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#WangQDWCLLWY21 %@ 978-4-86348-780-2

@inproceedings{conf/vlsic/WangQDWCLLWY21, added-at = {2022-08-10T00:00:00.000+0200}, author = {Wang, Yang and Qin, Yubin and Deng, Dazheng and Wei, Jingchuan and Chen, Tianbao and Lin, Xinhan and Liu, Leibo and Wei, Shaojun and Yin, Shouyi}, biburl = {https://www.bibsonomy.org/bibtex/26ea421eff54dfddaf4bc6aad960f7c1c/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2021}, ee = {https://doi.org/10.23919/VLSICircuits52068.2021.9492420}, interhash = {3c1befdb53c9295b742d2a3284e2c73a}, intrahash = {6ea421eff54dfddaf4bc6aad960f7c1c}, isbn = {978-4-86348-780-2}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T21:13:43.000+0200}, title = {A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#WangQDWCLLWY21}, year = 2021 }